Conventional memory architectures used in computing platforms rely on use of two elements: a memory controller and one or more memory modules that stores data accessed by the memory controller. In many conventional applications, the memory modules are typically industry standard memory modules having electrical interfaces, protocols, and mechanical fit and form defined by JEDEC (Joint Electronic Devices Engineering Council), a standards body.
As memory performance has improved over time, corresponding interface speeds between the memory controller and corresponding modules have also increased. Corresponding signaling voltages of the interfaces have decreased over time. Each performance improvement thus makes printed circuit board design (e.g., layout of traces connecting pins of each component) more challenging. That is, trace layouts tend to be more difficult for each memory speed improvement.
The JEDEC standards committee has acknowledged this increasing difficulty by incorporating (into the memory standards) a reduction in size of the maximum acceptable physical trace lengths and reduction of a number of cohabiting memory modules connected to the same access interface. Both of these changes reduce overall signal loading for a respective trace so that high access speeds are possible.